This application claims priority to Korean Patent Application No. 10-2004-0072107, filed on Sep. 9, 2004, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein, in its entirety, by reference.
1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, to an address coding method for reducing sensing noise during refresh and to an address decoder for performing the same.
2. Description of Related Art
In dynamic random access memory devices (DRAMs), periodic memory cell data refresh is important. If a refresh operation is not performed periodically, charge leakage from memory cells can result in data loss.
As the capacity of DRAM increases, a time needed for refreshing increases. Accordingly, effects of increased refresh time on the performance of a DRAM system should be considered. Since the refresh operation of a DRAM is generally controlled by a memory controller, and the like, a time consumed by the memory controller for requesting a refresh operation increases, and may exceed a time allocated to a normal operation.
In high-capacity DRAM, “multi-bank” and “pre-fetch” architectures have been introduced for performing refresh operations. In a multi-bank system, it is possible to significantly reduce an access time through an interleave operation for partially overlapping a plurality of banks, each with a different row address.
Due to the increase in the operation speed of the DRAM, a difference between a data transmission speed on internal data paths and a data transmission speed between the DRAM and interfaces becomes greater. For example, for a DRAM operating at 1.6 Gbps, the data transfer rate is 1.6 Gbps at the external interface of DRAM. The external interface of DRAM performs data transfer operation without missing the data. Since the internal data paths perform complicated operations such as various calculations, amplification, and coding, the internal data paths cannot operate at a high speed such as 1.6 Gbps (or 1.6 GHz). For this reason, a pre-fetch method for processing data in parallel enables a reduced internal operation speed of the DRAM to be used. For example, the pre-fetch method processes 8 pieces of data in parallel, and serially arranges and outputs the processed data. Accordingly, the DRAM can internally operate at 200 MHz while an external interface thereof operates at 1.6 GHz.
In DRAMs, having a number of banks and a number of the pre-fetches, a bank is shared by a plurality of memory blocks. Here, each bank has its unique row control block and each memory block has its unique data path. FIG. 1 is a view for explaining a memory device 100 having memory blocks with a conventional multi-bank structure. Referring to FIG. 1, bank groups BANK0–BANK3 and BANK4–BANK7 are shared by upper and lower memory blocks 110–120 and 130–140, respectively. In detail, first through fourth banks BANK0–BANK3 are shared by first and second memory blocks 110 and 120, and fifth through eighth banks BANK4–BANK7 are shared by third and fourth memory blocks 130 and 140.
Assume that a most significant bit (MSB) of a row address signal for allocating each of the banks BANK0–BANK7 to one of the upper and lower memory blocks 110–120 and 130–140, is RA12, as shown in FIG. 2, ones of banks BANK0–BANK7 to be shared by the upper first and third memory blocks 110 and 130 are addressed by a row address signal with an MSB of RA12 (“12”) and the others of the banks BANK0–BANK7 to be shared by the lower second and fourth memory blocks 120 and 140 are addressed by a row address signal with an MSB of RA12 (“ 12”). Since each of the banks BANK0–BANK7 is activated by a different row address signal, only one bank is activated during a normal operation, such as a read or write operation. However, during the refresh operation of the memory device 100, to reduce a time consumed for the refresh operation, all banks are activated to refresh memory cell data. Accordingly, as shown in FIG. 3, all of the banks BANK0–BANK7 shared by the upper first and third memory blocks 110 and 130 are activated to enable predetermined word lines 300 through 307. However, this method increases sensing noise since power consumption becomes non-uniform during the refresh operation.